vrahane commented on code in PR #3321:
URL: https://github.com/apache/mynewt-core/pull/3321#discussion_r1817436691
##########
hw/mcu/dialog/da1469x/src/da1469x_clock.c:
##########
@@ -29,39 +29,92 @@
#define XTAL32M_FREQ 32000000
#define RC32M_FREQ 32000000
+#define RC32M_FREQ_MIN 30600000
+#define RC32M_FREQ_MAX 32600000
+#define DIVN_FREQ 32000000 /* For CLK_CTRL_REG::SYS_CLK_SEL != 2 (LP
clock) */
+#define CAL_REF_FREQ DIVN_FREQ /* For CLK_REF_SEL_REG::CAL_CLK_SEL = 0
(DivN) */
#define PLL_FREQ 96000000
#define XTAL32K_FREQ 32768
+#define XTALRDY_IRQ_FREQ 256000 /* For XTALRDY_CTRL_REG::XTALRDY_CLK_SEL =
1 (256 kHz) */
+
+#define RC32M_CAL_REF_CNT 100
+
+#define XTALRDY_IRQ_DIV (RC32M_FREQ / XTALRDY_IRQ_FREQ)
+#define XTALRDY_IRQ_FREQ_MAX (RC32M_FREQ_MAX / XTALRDY_IRQ_DIV)
+
+#define RTC_IN_FREQ_HZ 100
+#define RTC_DIV_FRAC_ADJ 10 /* For CLK_RTCDIV_REG::RTC_DIV_DENOM = 0
(1000) */
static uint32_t g_mcu_clock_rcx_freq;
static uint32_t g_mcu_clock_rc32k_freq;
-static uint32_t g_mcu_clock_rc32m_freq;
+static uint32_t g_mcu_clock_xtal32k_freq;
+static uint32_t g_mcu_clock_rc32m_freq = RC32M_FREQ;
uint32_t SystemCoreClock = RC32M_FREQ;
+enum da1469x_sys_clk_sel {
+ DA1469X_SYS_XTAL32M = 0,
+ DA1469X_SYS_RC32M,
+ DA1469X_SYS_LP_CLK,
+ DA1469X_SYS_PLL96M,
+};
+
+enum da1469x_xtalrdy_clk_sel {
+ DA1469X_XTALRDY_CLK_32K = 0,
+ DA1469X_XTALRDY_CLK_256K,
+};
+#define DA1469X_XTALRDY_CLK_SEL DA1469X_XTALRDY_CLK_256K
+
+enum da1469x_lp_clk_sel {
+ DA1469X_LP_RC32K = 0,
+ DA1469X_LP_RCX,
+ DA1469X_LP_XTAL32K,
+ DA1469X_LP_EXT,
+};
+
+enum da1469x_ref_sel {
+ DA1469X_REF_DIVN = 0,
+ DA1469X_REF_RC32M,
+ DA1469X_REF_RC32K,
+ DA1469X_REF_XTAL32K,
+ DA1469X_REF_RCOSC,
+};
+#define DA1469X_REF_SEL DA1469X_REF_DIVN
+
+enum da1469x_calib_sel {
+ DA1469X_CALIB_RC32K = 0,
+ DA1469X_CALIB_RC32M,
+ DA1469X_CALIB_XTAL32K,
+ DA1469X_CALIB_RCX,
+ DA1469X_CALIB_RCOSC,
+};
+
+enum da1469x_rtc_div_denom_sel {
+ DA1469X_RTC_DIV_DENOM_1000 = 0,
+ DA1469X_RTC_DIV_DENOM_1024,
+};
+#define DA1469X_RTC_DIV_DENOM_SEL DA1469X_RTC_DIV_DENOM_1000
+
static inline bool
da1469x_clock_is_xtal32m_settled(void)
{
- return ((*(uint32_t *)0x5001001c & 0xff00) == 0) &&
- ((*(uint32_t *)0x50010054 & 0x000f) != 0xb);
+ return ((CRG_XTAL->XTALRDY_STAT_REG &
CRG_XTAL_XTALRDY_STAT_REG_XTALRDY_COUNT_Msk) == 0) &&
+ ((CRG_XTAL->XTAL32M_STAT1_REG &
CRG_XTAL_XTAL32M_STAT1_REG_XTAL32M_STATE_Msk) != 0xb);
}
void
da1469x_clock_sys_xtal32m_init(void)
{
- uint32_t reg;
int xtalrdy_cnt;
/*
- * Number of 256kHz clock cycles (~4.085us) assuming worst case when
actual frequency is 244800.
- * RC32M is in range <30.6, 32.6> so 256Khz can ba as low as 30.6MHz / 125
= 244.8kHz.
+ * Number of XTALRDY IRQ timer clock cycles making up the desired xtal
settling time,
+ * sufficient even at maximum RC32M frequency.
*/
- xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) * 1000 / 4085;
+ xtalrdy_cnt = MYNEWT_VAL(MCU_CLOCK_XTAL32M_SETTLE_TIME_US) *
XTALRDY_IRQ_FREQ_MAX / 1000000;
- reg = CRG_XTAL->XTALRDY_CTRL_REG;
- reg &= ~(CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk);
- reg |= CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CLK_SEL_Msk;
- reg |= xtalrdy_cnt;
- CRG_XTAL->XTALRDY_CTRL_REG = reg;
+ CRG_XTAL->XTALRDY_CTRL_REG = (xtalrdy_cnt <<
CRG_XTAL_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos) |
Review Comment:
nit-pick: nothing major, I think we should use the masks here specially
because values are coming from a syscfg.
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