[Nouveau] [PATCH] drm/nv50: wait for fifo completion in nv50_display_init

[Maxime COSTE]

Actually the only needed RING_WAIT is in nv50_display.

---
 drivers/gpu/drm/nouveau/nouveau_dma.h  |    8 ++++++++
 drivers/gpu/drm/nouveau/nv50_display.c |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h 
b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 9498c45..399436f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -128,6 +128,14 @@ FIRE_RING(struct nouveau_channel *chan)
 }
 
 static inline void
+RING_WAIT(struct nouveau_channel *chan)
+{
+       nouveau_wait_until(chan->dev, 2000000000ULL, 
+               NV50_PDISPLAY_USER_GET(0), 0xffffffff,
+               (chan->dma.cur << 2) + chan->pushbuf_base);
+}
+
+static inline void
 WIND_RING(struct nouveau_channel *chan)
 {
        chan->dma.cur = chan->dma.put;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c 
b/drivers/gpu/drm/nouveau/nv50_display.c
index 5c38c78..16b94d7 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -242,6 +242,7 @@ nv50_display_init(struct drm_device *dev)
        BEGIN_RING(&evo->chan, 0, NV50_CRTC0_UNK82C, 1);
        OUT_RING  (&evo->chan, 0);
        FIRE_RING (&evo->chan);
+       RING_WAIT (&evo->chan);
 
        /* enable clock change interrupts. */
        nv_wr32(NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
-- 
1.6.3.3


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