Francisco Jerez <[email protected]> writes: > Jimmy Rentz <[email protected]> writes: > >> On Fri, 11 Dec 2009 19:33:22 +0100 >> >> Have you looked at 0xB000, 0xB004, 0xB008 by chance? >> I noticed that nv uses these tiling regs (what looks like) on nv4a/nv4e >> (NV44 core) cards but not any others at startup. I thought is was because >> 0x406900 regs are missing. > > Yeah, I've seen the blob use those regs in some nv4a mmiotraces, but it > seemed to work without them and they're outside PGRAPH/PFB or anything > we currently exercise so I decided to leave them out. > >> >> +#define NV40_PFB_TILE2(i) (0x0000B000 + >> (i*12)) >> +#define NV40_PFB_TILE__SIZE_2 12 >> +#define NV40_PFB_TLIMIT2(i) (0x0000B004 + >> (i*12)) >> +#define NV40_PFB_TSIZE2(i) (0x0000B008 + >> (i*12))
Sorry for not replying-to-all the first time...
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