Trivially adds SEQ, SGT, SLE, SNE, SFL, STR and SSG which were missing.
Changed to preserv alphabetic order of cases.
---
src/gallium/drivers/nv40/nv40_vertprog.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c
b/src/gallium/drivers/nv40/nv40_vertprog.c
index 80f2a87..2f86e64 100644
--- a/src/gallium/drivers/nv40/nv40_vertprog.c
+++ b/src/gallium/drivers/nv40/nv40_vertprog.c
@@ -545,12 +545,33 @@ nv40_vertprog_parse_instruction(struct nv40_vpc *vpc,
case TGSI_OPCODE_RSQ:
arith(vpc, 1, OP_RSQ, dst, mask, none, none, abs(src[0]));
break;
+ case TGSI_OPCODE_SEQ:
+ arith(vpc, 0, OP_SEQ, dst, mask, src[0], src[1], none);
+ break;
+ case TGSI_OPCODE_SFL:
+ arith(vpc, 0, OP_SFL, dst, mask, src[0], src[1], none);
+ break;
case TGSI_OPCODE_SGE:
arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
break;
+ case TGSI_OPCODE_SGT:
+ arith(vpc, 0, OP_SGT, dst, mask, src[0], src[1], none);
+ break;
+ case TGSI_OPCODE_SLE:
+ arith(vpc, 0, OP_SLE, dst, mask, src[0], src[1], none);
+ break;
case TGSI_OPCODE_SLT:
arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
break;
+ case TGSI_OPCODE_SNE:
+ arith(vpc, 0, OP_SNE, dst, mask, src[0], src[1], none);
+ break;
+ case TGSI_OPCODE_SSG:
+ arith(vpc, 0, OP_SSG, dst, mask, src[0], src[1], none);
+ break;
+ case TGSI_OPCODE_STR:
+ arith(vpc, 0, OP_STR, dst, mask, src[0], src[1], none);
+ break;
case TGSI_OPCODE_SUB:
arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
break;
--
1.6.3.3
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