Mario Kleiner <[email protected]> writes: > On 12/29/2010 10:44 AM, Ben Skeggs wrote: >> On Wed, 2010-12-29 at 10:37 +0100, Maarten Maathuis wrote: >>[...] >>> >>> In my infinite wisdom i swapped the vertical and horizontal regs, >>> these are the right ones: >>> >>> 0x616340: CRTC0 horizontal scanline (lower 16 bits, upper 16 bits is a >>> counter that increments every display cycle) >>> 0x616344: CRTC0 vertical scanline (lower 16 bits, upper 16 bits empty) >>> >>> 0x616B40: CRTC1 horizontal scanline >>> 0x616B44: CRTC1 vertical scanline >> Ah, I should've waited 10 minutes before doing the same here. Ah well, >> I can confirm at least on NV84, I can't imagine it differs at all on any >> nv50+ board either. >>
I can confirm those registers are still there on NVA8. >> Ben. >>> > > Wow, that was fast! Thanks! I'll get some good sleep now and then give > it a try on my GF-8800. This is probably also useful to implement the > .get_vblank_counter() hook properly. Currently it hooks up to > drm_vblank_count() which is problematic, as .get_vblank_counter() is > meant to query the hardware for the purpose of reinitializing > drm_vblank_count() after a long vblank irq off period. > > I'll let you know how it goes, hopefully with some nice patches asap. > > If somebody knows about similar NV40 and earlier registers, keep it > coming :-) > On nv04-nv4x class hardware there's a scanline counter in the lower 12 bits of 0x600808 (0x602808 for the second CRTC), bit 16 lights up during the vblank period. I don't think I've ever seen a hardware frame counter there, but they might have one. Tracing what the nvidia blob does for SGI_video_sync and friends would be your best bet I guess. > Is the range from NV_PCRTC0_OFFSET to NV_PCRTC0_OFFSET + > NV_PCRTC0_SIZE a good starting point for a search on NV40 and earlier? > > thanks, > -mario > _______________________________________________ > Nouveau mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/nouveau
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