Francisco Jerez <[email protected]> writes: > Mario Kleiner <[email protected]> writes: > >> On 09/09/2011 11:14 PM, Francisco Jerez wrote: >>> Mario Kleiner<[email protected]> writes: >>> >>>>[...] >>>> Is the blip operation started at leading edge of the vblank interval? >>>> Or anywhere inside the vblank interval (level triggered)? Are such >>>> blits submitted on a separate fifo (or even dma engine?) in the gpu to >>>> avoid stalling the rest of the command stream until vblank? >>> >>> It depends, right now we have two completely different implementations >>> and we use one or the other depending on the card generation: >>> >>> On nv11-nv4x, we use the PGRAPH vsync methods (0x120-0x134), that means >>> it's the drawing engine that waits. Basically you have a counter that's >>> incremented by a CRTC of your choice when it reaches a scanline range of >>> your choice, wrapping around at a configurable value; you can put the >>> drawing engine to sleep until the counter reaches a given value. Right >>> now we make it wait until somewhere between vdisplay-3 and vdisplay-1 >>> before going on with the swap. >>> >> >> Interesting, thanks for the explanation. Maybe that counter could also >> be used to implement a hardware vblank counter on pre-NV50?
I forgot to answer to this question... Not really, these counters are (IIRC) only 3 bits wide, and they need PGRAPH intervention to get incremented, so they're quite useless for anything more sophisticated than what we're doing right now. >>[...]
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