Generally following Nvidia here, but being more focused on the load groups.
Signed-off-by: Karol Herbst <karolher...@gmail.com>
---
drm/nouveau/include/nvkm/subdev/pmu.h | 9 ++++++++
drm/nouveau/nvkm/subdev/pmu/gt215.c | 43 +++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/drm/nouveau/include/nvkm/subdev/pmu.h
b/drm/nouveau/include/nvkm/subdev/pmu.h
index e7f04732..b29570eb 100644
--- a/drm/nouveau/include/nvkm/subdev/pmu.h
+++ b/drm/nouveau/include/nvkm/subdev/pmu.h
@@ -26,6 +26,15 @@ struct nvkm_pmu {
} recv;
};
+enum nvkm_pmu_counter_slot {
+ NVKM_PMU_COUNTER_SLOT_TOTAL = 0,
+ NVKM_PMU_COUNTER_SLOT_CORE = 1,
+ NVKM_PMU_COUNTER_SLOT_MEMORY = 2,
+ NVKM_PMU_COUNTER_SLOT_VIDEO = 3,
+ NVKM_PMU_COUNTER_SLOT_PCIE = 4,
+ NVKM_PMU_COUNTER_SLOT_LAST = 8, // we support up to 8 slots for now
+};
+
int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process,
u32 message, u32 data0, u32 data1);
void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable);
diff --git a/drm/nouveau/nvkm/subdev/pmu/gt215.c
b/drm/nouveau/nvkm/subdev/pmu/gt215.c
index 4bead2b7..b7053cf7 100644
--- a/drm/nouveau/nvkm/subdev/pmu/gt215.c
+++ b/drm/nouveau/nvkm/subdev/pmu/gt215.c
@@ -26,6 +26,48 @@
#include <subdev/timer.h>
+static void
+gt215_setup_pmu_counters(struct nvkm_pmu *pmu)
+{
+ struct nvkm_device *device = pmu->subdev.device;
+ u32 core_mask = 0;
+ u32 video_mask = 0;
+ u32 memory_mask = 0;
+
+ if (nvkm_device_engine(device, NVKM_ENGINE_GR))
+ core_mask |= 0x00000001;
+ if (nvkm_device_engine(device, NVKM_ENGINE_CE0))
+ core_mask |= 0x00080000;
+ if (nvkm_device_engine(device, NVKM_ENGINE_CE1))
+ core_mask |= 0x00100000;
+ if (nvkm_device_engine(device, NVKM_ENGINE_CE2))
+ core_mask |= 0x00200000;
+
+ if (nvkm_device_engine(device, NVKM_ENGINE_MSVLD))
+ video_mask |= 0x00000010;
+ if (nvkm_device_engine(device, NVKM_ENGINE_MSPDEC))
+ video_mask |= 0x00000020;
+ if (nvkm_device_engine(device, NVKM_ENGINE_MSPPP))
+ video_mask |= 0x00000040;
+ if (nvkm_device_engine(device, NVKM_ENGINE_NVENC0))
+ video_mask |= 0x00020000;
+
+ if (device->chipset < 0xc0)
+ memory_mask = 0x100;
+ else
+ memory_mask = 0x80;
+
+ nvkm_pmu_send(pmu, NULL, PROC_PERF, PERF_MSG_SET_SLOT,
+ NVKM_PMU_COUNTER_SLOT_CORE, core_mask);
+ nvkm_pmu_send(pmu, NULL, PROC_PERF, PERF_MSG_SET_SLOT,
+ NVKM_PMU_COUNTER_SLOT_VIDEO, video_mask);
+ nvkm_pmu_send(pmu, NULL, PROC_PERF, PERF_MSG_SET_SLOT,
+ NVKM_PMU_COUNTER_SLOT_MEMORY, memory_mask);
+ if (pmu->func->counter_slots >= NVKM_PMU_COUNTER_SLOT_PCIE)
+ nvkm_pmu_send(pmu, NULL, PROC_PERF, PERF_MSG_SET_SLOT,
+ NVKM_PMU_COUNTER_SLOT_PCIE, 0x20000000);
+}
+
int
gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
u32 process, u32 message, u32 data0, u32 data1)
@@ -232,6 +274,7 @@ gt215_pmu_init(struct nvkm_pmu *pmu)
pmu->recv.size = nvkm_rd32(device, 0x10a4dc) >> 16;
nvkm_wr32(device, 0x10a010, 0x000000e0);
+ gt215_setup_pmu_counters(pmu);
return 0;
}
--
2.13.0
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