[Nouveau] [PATCH v2 4/4] drm/amdgpu: Support allocate of amdgpu_gtt_mgr from pages to bytes

[Somalapuram Amaranath]

Change the GTT manager init and allocate from pages to bytes
v1 -> v2: reorder patch sequence

Signed-off-by: Somalapuram Amaranath <amaranath.somalapu...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 44367f03316f..a1fbfc5984d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
                              struct ttm_resource **res)
 {
        struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
-       uint32_t num_pages = PFN_UP(tbo->base.size);
        struct ttm_range_mgr_node *node;
        int r;
 
@@ -134,8 +133,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
        if (place->lpfn) {
                spin_lock(&mgr->lock);
                r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
-                                               num_pages, tbo->page_alignment,
-                                               0, place->fpfn, place->lpfn,
+                                               tbo->base.size,
+                                               tbo->page_alignment << 
PAGE_SHIFT, 0,
+                                               place->fpfn << PAGE_SHIFT,
+                                               place->lpfn << PAGE_SHIFT,
                                                DRM_MM_INSERT_BEST);
                spin_unlock(&mgr->lock);
                if (unlikely(r))
@@ -144,7 +145,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
                node->base.start = node->mm_nodes[0].start;
        } else {
                node->mm_nodes[0].start = 0;
-               node->mm_nodes[0].size = PFN_UP(node->base.size);
+               node->mm_nodes[0].size = node->base.size;
                node->base.start = AMDGPU_BO_INVALID_OFFSET;
        }
 
@@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, 
uint64_t gtt_size)
 
        ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
 
-       start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
-       size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+       start = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 
AMDGPU_GTT_NUM_TRANSFER_WINDOWS) << PAGE_SHIFT;
+       size = adev->gmc.gart_size - start;
        drm_mm_init(&mgr->mm, start, size);
        spin_lock_init(&mgr->lock);
 
-- 
2.32.0