Change the signature of the program_brom HAL method to not return anything. None of the implementations can actually fail, so they always return Ok(()).
Signed-off-by: Timur Tabi <[email protected]> --- drivers/gpu/nova-core/falcon.rs | 2 +- drivers/gpu/nova-core/falcon/hal.rs | 2 +- drivers/gpu/nova-core/falcon/hal/ga102.rs | 8 +++----- drivers/gpu/nova-core/falcon/hal/tu102.rs | 4 +--- 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 37bfee1d0949..14a789ac625a 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -532,7 +532,7 @@ fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_params())?; self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params())?; - self.hal.program_brom(self, bar, &fw.brom_params())?; + self.hal.program_brom(self, bar, &fw.brom_params()); // Set `BootVec` to start of non-secure code. regs::NV_PFALCON_FALCON_BOOTVEC::default() diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/falcon/hal.rs index 89babd5f9325..c8480e8afe0b 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -46,7 +46,7 @@ fn signature_reg_fuse_version( ) -> Result<u32>; /// Program the boot ROM registers prior to starting a secure firmware. - fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result; + fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams); /// Check if the RISC-V core is active. /// Returns `true` if the RISC-V core is active, `false` otherwise. diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs index 8f62df10da0a..478823311c83 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -75,7 +75,7 @@ fn signature_reg_fuse_version_ga102( Ok(u16::BITS - reg_fuse_version.leading_zeros()) } -fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> Result { +fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) { regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default() .set_value(params.pkc_data_offset) .write(bar, &E::ID, 0); @@ -88,8 +88,6 @@ fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> regs::NV_PFALCON2_FALCON_MOD_SEL::default() .set_algo(FalconModSelAlgo::Rsa3k) .write(bar, &E::ID); - - Ok(()) } pub(super) struct Ga102<E: FalconEngine>(PhantomData<E>); @@ -115,8 +113,8 @@ fn signature_reg_fuse_version( signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_mask, ucode_id) } - fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result { - program_brom_ga102::<E>(bar, params) + fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) { + program_brom_ga102::<E>(bar, params); } fn is_riscv_active(&self, bar: &Bar0) -> bool { diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs index 7de6f24cc0a0..c38a556d1565 100644 --- a/drivers/gpu/nova-core/falcon/hal/tu102.rs +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -44,9 +44,7 @@ fn signature_reg_fuse_version( Ok(0) } - fn program_brom(&self, _falcon: &Falcon<E>, _bar: &Bar0, _params: &FalconBromParams) -> Result { - Ok(()) - } + fn program_brom(&self, _falcon: &Falcon<E>, _bar: &Bar0, _params: &FalconBromParams) {} fn is_riscv_active(&self, bar: &Bar0) -> bool { let cpuctl = regs::NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS::read(bar, &E::ID); base-commit: cea7b66a80412e2a5b74627b89ae25f1d0110a4b -- 2.52.0
