On Thu, 2026-02-05 at 20:21 -0800, John Hubbard wrote: > +/// EMEM control register bit 24: write mode. > +const EMEM_CTL_WRITE: u32 = 1 << 24; > +/// EMEM control register bit 25: read mode. > +const EMEM_CTL_READ: u32 = 1 << 25; > +
Shouldn't these be bits in the NV_PFALCON_FALCON_EMEM_CTL register instead?
