On Tue Feb 10, 2026 at 3:45 AM CET, John Hubbard wrote:
> + pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 {
> + pub(crate) fn send_msg(&self, bar: &Bar0, packet: &[u8]) -> Result {
> + pub(crate) fn recv_msg(&self, bar: &Bar0, buffer: &mut [u8], size:
> usize) -> Result<usize> {
Just a quick note, since I just reminded myself on this: We should keep in mind
that at some point we have to replace most (if not all) &Bar0 usages with
&Mmio<SIZE> as nova-core will also support platform devices.
I think Tegra chips with GSP-based GPU IPs have a compatible register layout,
right?
(I will prepare a patch to address this for the existing codebase.)
