Add TLB (Translation Lookaside Buffer) flush support for GPU MMU. After modifying page table entries, the GPU's TLB must be invalidated to ensure the new mappings take effect. The Tlb struct provides flush functionality through BAR0 registers.
The flush operation writes the page directory base address and triggers an invalidation, polling for completion with a 2 second timeout matching the Nouveau driver. Cc: Nikola Djukic <[email protected]> Signed-off-by: Joel Fernandes <[email protected]> --- drivers/gpu/nova-core/mm/mod.rs | 1 + drivers/gpu/nova-core/mm/tlb.rs | 92 +++++++++++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 33 ++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/tlb.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod.rs index c88b7b7b6975..eafd56964b1b 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -6,6 +6,7 @@ pub(crate) mod pagetable; pub(crate) mod pramin; +pub(crate) mod tlb; use kernel::sizes::SZ_4K; diff --git a/drivers/gpu/nova-core/mm/tlb.rs b/drivers/gpu/nova-core/mm/tlb.rs new file mode 100644 index 000000000000..466c7731323e --- /dev/null +++ b/drivers/gpu/nova-core/mm/tlb.rs @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! TLB (Translation Lookaside Buffer) flush support for GPU MMU. +//! +//! After modifying page table entries, the GPU's TLB must be flushed to +//! ensure the new mappings take effect. This module provides TLB flush +//! functionality for virtual memory managers. +//! +//! # Example +//! +//! ```ignore +//! use crate::mm::tlb::Tlb; +//! +//! fn page_table_update(tlb: &Tlb, pdb_addr: VramAddress) -> Result<()> { +//! // ... modify page tables ... +//! +//! // Flush TLB to make changes visible (polls for completion). +//! tlb.flush(pdb_addr)?; +//! +//! Ok(()) +//! } +//! ``` + +#![allow(dead_code)] + +use kernel::{ + devres::Devres, + io::poll::read_poll_timeout, + new_mutex, + prelude::*, + sync::{Arc, Mutex}, + time::Delta, // +}; + +use crate::{ + driver::Bar0, + mm::VramAddress, + regs, // +}; + +/// TLB manager for GPU translation buffer operations. +#[pin_data] +pub(crate) struct Tlb { + bar: Arc<Devres<Bar0>>, + /// TLB flush serialization lock: This lock is acquired during the + /// DMA fence signalling critical path. It must NEVER be held across any + /// reclaimable CPU memory allocations because the memory reclaim path can + /// call `dma_fence_wait()`, which would deadlock with this lock held. + #[pin] + lock: Mutex<()>, +} + +impl Tlb { + /// Create a new TLB manager. + pub(super) fn new(bar: Arc<Devres<Bar0>>) -> impl PinInit<Self> { + pin_init!(Self { + bar, + lock <- new_mutex!((), "tlb_flush"), + }) + } + + /// Flush the GPU TLB for a specific page directory base. + /// + /// This invalidates all TLB entries associated with the given PDB address. + /// Must be called after modifying page table entries to ensure the GPU sees + /// the updated mappings. + pub(crate) fn flush(&self, pdb_addr: VramAddress) -> Result { + let _guard = self.lock.lock(); + + let bar = self.bar.try_access().ok_or(ENODEV)?; + + // Write PDB address. + regs::NV_TLB_FLUSH_PDB_LO::from_pdb_addr(pdb_addr.raw_u64()).write(&*bar); + regs::NV_TLB_FLUSH_PDB_HI::from_pdb_addr(pdb_addr.raw_u64()).write(&*bar); + + // Trigger flush: invalidate all pages and enable. + regs::NV_TLB_FLUSH_CTRL::default() + .set_page_all(true) + .set_enable(true) + .write(&*bar); + + // Poll for completion - enable bit clears when flush is done. + read_poll_timeout( + || Ok(regs::NV_TLB_FLUSH_CTRL::read(&*bar)), + |ctrl| !ctrl.enable(), + Delta::ZERO, + Delta::from_secs(2), + )?; + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index d0982e346f74..c948f961f307 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -454,3 +454,36 @@ pub(crate) mod ga100 { 0:0 display_disabled as bool; }); } + +// MMU TLB + +register!(NV_TLB_FLUSH_PDB_LO @ 0x00b830a0, "TLB flush register: PDB address bits [39:8]" { + 31:0 pdb_lo as u32, "PDB address bits [39:8]"; +}); + +impl NV_TLB_FLUSH_PDB_LO { + /// Create a register value from a PDB address. + /// + /// Extracts bits [39:8] of the address and shifts it right by 8 bits. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::default().set_pdb_lo(((addr >> 8) & 0xFFFF_FFFF) as u32) + } +} + +register!(NV_TLB_FLUSH_PDB_HI @ 0x00b830a4, "TLB flush register: PDB address bits [47:40]" { + 7:0 pdb_hi as u8, "PDB address bits [47:40]"; +}); + +impl NV_TLB_FLUSH_PDB_HI { + /// Create a register value from a PDB address. + /// + /// Extracts bits [47:40] of the address and shifts it right by 40 bits. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::default().set_pdb_hi(((addr >> 40) & 0xFF) as u8) + } +} + +register!(NV_TLB_FLUSH_CTRL @ 0x00b830b0, "TLB flush control register" { + 0:0 page_all as bool, "Invalidate all pages"; + 31:31 enable as bool, "Enable/trigger flush (clears when flush completes)"; +}); -- 2.34.1
