Author: Daniel Ice <[email protected]>
Repository: /hg/onnv/onnv-gate
Latest revision: e4f9a0025b499cad963f53e50bc772db9ca81ebe
Total changesets: 1
Log message:
6896094 For Intel 41210 PCIe2PCI Bridge, MPS for F0 and F2 should be
initialized at the same time
Files:
update: usr/src/uts/common/io/pciex/pcie.c
update: usr/src/uts/common/io/pciex/pcieb.c
update: usr/src/uts/common/io/pciex/pcieb.h
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