Hi Timothy,

On Wednesday 23 February 2005 18:37, Timothy Miller wrote:
> What we want to do is design an FPGA board that is relatively large
> and has lots of test points for debugging, 

Real men don't use test points :-)

Seriously, I'd much prefer that the FPGA board is as much like the ASIC 
card as possible.  OK, it doesn't have to be half-height any more, but 
if it can be, why not?  We don't have to fret any more about not having 
a separate VGA on it.  The AGP version can go away forever.  The PCI-E 
version recedes into the future, since the PCI version is going to 
allow more developers on board sooner.

The development card is going to be available way before the ASIC.  
There will be people buying it just to do multihead and things like 
that.  In fact, all the things we originally planned.  Perhaps not 
10,000 but more than likely in the thousands.  There's quite a lot of 
suppressed demand out there.

Here is a summary of changes I'd like to see, which were all discussed 
in the thread:

  - Protect the PCI interface somehow so that no matter what happens the
    FPGA can still be reloaded via PCI.  Actually, I would not mind at
    all if this requires attaching a button to the card and pushing it,
    or similar. Normally, the PCI logic isn't going to get messed up,
    even if everything else does.

  - Support reprogram/reset entirely under software control.

  - Use the bigger FPGA if it's available and isn't outrageously
    expensive and doesn't melt the card.

But above all:

  - Please keep it light and tight.

It's the principle of the thing, if nothing else.  I would be highly 
uninterested in seeing LED readouts and pushbuttons on the card, like 
the one somebody linked.  It should still be first and foremost a 
usable graphics card, just one that happens to be reprogrammable.

> while the ASIC board is small and inexpensive. Sometimes you spend a
> little more now in order to insulate yourself against catastropic
> expenses in the future.  Spending $100k extra now in order to ensure
> that we don't have to spend another $1 million on an ASIC respin is
> well worth the cost. 

Putting on my MBA hat, it could well turn out to be a brilliant strategy 
for tightening up the quality circle and cutting both development costs 
and time to market.

Regards,

Daniel
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