On Thu, 17 Mar 2005 19:51:42 -0500, Daniel Phillips <[EMAIL PROTECTED]> wrote:
> That's it: three PIO registers, two command/status bits and a four-bit > command/status field. We press the cursor upload mechanism into double > duty, a nicety I'm rather fond of. You keep mentioning the cursor. The cursor is only one of numerous things that will be accessible via PIO. All engine registers (for reading), the engine write fifo, debug, status, interrupt control, etc., etc. will be accessible via PIO. Basically, via PIO, you'll be able to access all priveleged and unpriveleged registers. The only reason DMA can't get at priveleged registers is because the command packets will always refer to registers implicitly. BTW, you'll also be able to put rendering command packets into the ring buffer. What protects against applications initiating DMA is that an indirect DMA request from an indirect DMA buffer is invalid, because the "stack" only goes one level deep (read: such commands will be silently dropped). _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
