On Friday 18 March 2005 04:49, Attila Kinali wrote: > On Thu, 17 Mar 2005 23:31:45 -0500 > > Timothy Miller <[EMAIL PROTECTED]> wrote: > > I wasn't clear. When I say that the GPU "polls the write pointer", I > > mean, "the GPU does a DMA read of a word in host memory that contains > > the write pointer". > > The pointer here is a 64 bit value, right ?
The write pointer he's talking about is a logical offset into the ring buffer, 32 bits I presume. Probably expressed in 32 bit words. > How do you garantee atomicity of the read ? > Ie i see here a race condition on 32 bit systems, > when the host updates the pointer. > > And how does it work with cache ? Ie, is the cache > flushed if the pci buss accesses a region of the > host memory which contents were modified in the cache ? The kernel takes care of flushing the data cache (a noop on x86) as part of the process of locking down a page for DMA. This page lockdown will be handled by our DRI kernel module, which implements the DRI's DMA setup methods. That said, I'm not sure DRI accommodates our (emerging) indirect DMA model, I'm drilling down into that now. I do agree with whoever said it, we're going a little beyond the status quo here, and that is a good thing. Everybody should read this: http://web.archive.org/web/20020206203642/http://www.precisioninsight.com/dr/security.html Regards, Daniel _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
