You are losing sight of the point behind this prototype card. The idea is for the hardware engineers and early testers to have a platform to work with that can be reprogrammed, probed, prodded, etc.
But no matter how much you strip off it, it's never going to be cheap, because the production volumes are going to be very small. Remember, we started with having a plan with no profit, where the FPGA-based boards would be sold basically at-cost, in volume so that we could build a brand identity for the next version. That didn't fly, so the new plan is to be profitable much earlier. That required focusing on the embedded space, designing an ASIC, and getting higher volumes. This puts the FPGA version on the back-burner in terms of cost-cutting, and in fact, cost-cutting HERE would do nothing but hurt the project. Those who buy it will be hard-code hobbyists and universities needing prototype boards. But the POINT behind the board is so that we end up with a relatively bug-free ASIC for the final product. Now, certainly, we don't have to populate all the parts on what we sell to the hobbyist, but that's not going to affect cost much. On Apr 5, 2005 6:40 PM, Daniel Phillips <[EMAIL PROTECTED]> wrote: > On Tuesday 05 April 2005 16:52, Timothy Miller wrote: > > Um... I'm really hesitant to do that. We did a parts cost estimate, > > but I can't remember the number off hand, although I think it was > > over $300. Note that this board would include a good number of > > "debug" features, since that's its primary purpose, and that > > increases cost. However, whatever it is, we have to price it > > appropriately for development and overhead. Naturally, we don't > > expect to sustain the business on it, but it does need to be > > profitable. > > I'm torn between wanting all the trimmings and wanting the price below > $200, for the _prototype_ board. Can we have a list of costly debug > features we can kick around? I know there are bits and pieces of > debate on this back there in the archives, but that's a long way back. > > I don't think we should lose sight of "light and tight" even for the > prototype board. That would compromise the ASIC. > I personally would not mind having to fall back to loading the fpga via > jtag if the pci logic gets accidently destroyed, and thus be able to > put the pci login on the fpga as originally planned. Does this save > anything significant? Maybe, about $10, and it would increase development costs. > I sure do not want blinking lights, led displays and that sort of thing. No, the debug stuff is mostly in having extra headers, test points, more pins on the FPGA than on the ASIC, non-integrated PCI controller, sparse layout of parts on the board, etc. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
