Le mercredi 20 Avril 2005 17:48, Timothy Miller a �crit : > On 4/20/05, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > > > There are some compromises we can make here for the sake of pin > > > savings. For instance, with a 30-bit address bus (plus four write > > > enables), the upper bits of the address change infrequently. We could > > > make the address bus 15 bits and have separate transactions for the > > > upper and lower bits. This way, when streaming data, there's one > > > upper-half transaction, followed by many lower-halfs. You'll get a > > > wasted cycle every 128K bytes to change the upper half. This also > > > gives us some room for optimizing the state machine for higher speeds. > > > I'll get into the specifics of the hand-shaking, as it progresses. > > > > Typical bus are horrible because of the read round trip (setup/hold > > timing, ...). So serial bus is much easier to do with better performance, > > and less static timing analysis headhack, IMHO. > > Yeah, I was looking at the Wishbone specification, and it requires a > combinatorial loop between devices in order to get full bandwidth. > > Our problem is that we have to go off-chip, which means there's no way > in hell we can have a combinatorial loop. Our interface MUST be > synchronous.
I think a Wishbone V2 use 2 cycle as AMBA. > > The cool thing is that the Opencores PCI core is under LGPL! [jumps > for joy] That means we can use it. Naturally, any improvements we > make, we'll resubmit. > It need some work. I have heard this core is not very good. > The advantage to using wishbone is that it's a standard, so people can > use that interface on what they put into the bigger FPGA. Still, > there may be cause to start over anyhow, to design something that has > a synchronous interface and is intended to run at much higher speeds > than what's on opencores. > > > Point to Point connections is the fastest connection. So you could use 32 > > bits for writing PCI to OGP and 16 bits from the OGP to the PCI chip > > (with one clock for each way ? So you could sample the input using those > > clock, and win some more time on the clock jitter and output delay). > > Oh, yeah. We're going to have a tolerance for length of traces between > chips. > yep. > > You have to define some "packet" format which include data and adresse. > > Basically you need 2 types of paquet one to minimise latency and one to > > maximise bandwith usage. > > > > What do you think of it ? > > What I think is that since the opencores PCI controller is under LGPL, > it's not off-limits. If list members could start looking at it to > help us figure it out (and wishbone too), that would help us out a > lot. This kind of bus look like hypertransport. But hypertransport is maybe an overkill for that chip (i think that there specification is open). Nicolas Boulay _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
