On Sun, May 01, 2005 at 09:31:49PM -0400, Timothy Miller wrote:
> > 1. Step 1 should be to document the register model of the target chip,
> > which is also the register model of the FPGA emulation, and freeze it. This
> > allows the hardware and software teams to decouple, so they can work
> > independently at their own pace. The first draft of the register model spec
> > gives each contingent something to check its design approaches against, to
> > see where refinements should be made from each side. Until everybody agrees
> > on this interface spec, detailed implementation work is likely to be wasted,
> > because the target is moving. This spec isn't done until all register
> > addresses and bit assignments are frozen, and everybody signs off.
>
> I'm working on that right now, although the work schedule has a number
> of other things higher priority. I'll see if I can squeeze in some
> more time on the register set earlier. We're working on a schedule to
> share, so we can discuss that.
>
> > 3. With the interfaces to both sides of the FPGA frozen, the Verilog code
> > can all be written, and synthesized to determine the size and number of
> > FPGAs required for implementation. (I got a big surprise here, when I took
> > my project leader's word for it, and designed the PCB to mount the FPGA he
> > chose. The logic didn't fit, and I had to do the board over to use a bigger
> > FPGA.)
>
> We're picking a footprint that works across multiple models, fortunately.
Sounds like we're thinking along the same lines. OK, I'll pipe down
until I have time to read into the project and have the background to
understand the discussions better.
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