On 5/12/05, Jack Carroll <[EMAIL PROTECTED]> wrote: > On Thu, May 12, 2005 at 04:13:49PM -0400, Timothy Miller wrote: > > On 5/12/05, Jack Carroll <[EMAIL PROTECTED]> wrote: > > [snip] > > > > > But I still don't see how trade secret protection is compatible > > > with > > > FPGA development in the field. Is it possible to add compiled logic to an > > > FPGA load image without revealing the HDL source code? > > [snip] > > > As for VGA, it's a noncritical part of the design that nevertheless > > requires a ton of work. In the spirit of really wanting to GPL the > > whole thing, I though it would be nice to just share it from the > > start. I got tons of help with the 3D renderer but won't be releasing > > the code for a while, but people who helped knew that from the start. > > If someone else fabs the VGA emulator, it won't hurt us. If someone > > else fabs the 3D engine, it could put us out of business. > > It sounds like this is starting to converge. > If the 3D engine is kept under trade secret protection for an > agreed-on length of time, and the length of time is known to all, that > should meet everybody's minimum needs so the project can continue. As some > politician once said, when all parties are equally dissatisfied, the deal is > probably fair.
I'm not dissatisfied by this idea. Maybe there's something wrong with it. :) > OK, I think this just leaves one technical question: during the time > some of the HDL is still under trade secret protection, is there any way a > non-privileged owner of an FPGA board can hack and synthesize the open > portions of the code, and then link it into a complete FPGA load image? I > probably ought to know the answer to that, but my VHDL experience is limited > to a few months, and that was almost 4 years ago. The interface to the > closed-source modules could be described in a specification, so if the > synthesized code can be delivered in a linkable format, it should be > possible. The RTL that will come with the FPGA board will include things like the PCI controller, a pad-ring for the Xilinx, a memory controller, a simple video controller, and probably a few other things that would make a useful starting point for any random project that someone would like to come up with. Also, it might be possible to provide a post-synthesis netlist of the closed part of the design for linking against. I know there are drop-in cores for FPGAs. But we'll have to figure out if the netlist is impenetrable enough. The bitfile will already be hackable to the most industrious of reverse engineer. The point is to protect the IP very well for a period of time to ensure the project's success, THEN release it completely, making cracking it pointless. The time you have to be patient could be measured in months. Lead time for parts can be longer than that sometimes. :) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
