On Mon, May 16, 2005 at 09:11:53PM -0400, Timothy Miller wrote:
>
> I feel like I should know what SPI is, and it sounds familiar, but I
> can't place it right off. Give me some details, and I'll see what I
> can do.
Right-o. Serial Peripheral Interface is, IMO, the simplest possible
I/O expansion interface for a microprocessor. It's pervasive in Motorola
embedded processors such as the 68HC05 family. One of its virtues is that
it doesn't require special-purpose peripheral interface ICs; off-the-shelf
shift registers of various configurations will do. My last design used
74HC164s and 74HC595s.
Typically, an SPI device has 4 main signals:
SCLK Serial clock
MOSI Master-out, slave-in serial data line
MISO Master-in, slave-out serial data line
!CEN Not Chip Enable
The master brings the enable line low for the serial chain to be
selected, places the first output data bit on MOSI, pulses SCLK, and reads
the first input data bit on MISO. This continues until all the bits have
been transferred. Typically, a master is hard-wired to transfer 8 bits with
a single instruction, by writing to the SPI data output register. Then it
reads the SPI data input register.
For a simple output chain where bit rippling can be tolerated, no
other signals are needed. If the output register chain is double-buffered,
the master needs to pulse a parallel transfer control line after all the
bits are sent. For an input chain, it's necessary to pulse a parallel-load
signal before clocking the data bits in.
A serial chain implemented with 74HC shift registers can usually
handle a clock rate of 30 MHz or so, but most of these low-end embedded
processors are limited to 10 MHz or less.
Since most shift registers have both serial inputs and serial
outputs, they can be strung together to make a chain of any length, without
adding to the number of control pins needed.
One stunt I pulled when I had a shortage of microprocessor port pins
and a lot of serial chains to poll was to dedicate one chain to enable bits
for the rest of the chains. That way, I only needed two chip enable lines
out of the microprocessor: one for the address register, and one for
whatever chain was selected. A lot of devices have two or more ANDed enable
lines, so this doesn't take extra glue logic.
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