On Tue, 2005-05-31 at 16:31 +0200, [EMAIL PROTECTED] wrote: > > I assume he's referring to a classic 5-stage design with a MEM stage: > > -fetch > > -decode > > -execute > > -memory access > > -register writeback > > > > Do you really need 5 stages ? 3 is not enought ? If data could enter in > few register you don't need a load&store unit.
I see no inherent reason it would have to be a 5-stage processor. I was just relating back to Hennessy & Patterson and MIPS as it seems to be the "classic" pipelining example. Timothy, however, seems to say we need 4+ stages to get clock rate up. I can't say I have much experience in timing/speed issues though, so I'll defer to him. With regards to your 3-stage processor: Is this a closed product? Don't we risk becoming encumbered by this? -Chip _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
