On 6/2/05, Peter TB Brett <[EMAIL PROTECTED]> wrote: > > Timothy Miller wrote: > > >> From my work on the XC3S1500 parts, I seem to remember that Xilinx > >> recommend connecting unused BRAM pins to pwr -- including the parity > >> bits if they're not used. > > > > Is that for power-consumption purposes? I usually just leave them > > unconnected. What does ISE do about unconnected I/Os? > > > > From XAPP463, "Using Block RAM in Spartan-3 Generation FPGAs, page 8: > > Unused Inputs > > Tie any unused data or address inputs to logic '1'. Connecting the unused > inputs High saves logic and routing resources compared to connecting the > inputs Low. > > I'm not _sure_ what ISE does with unused IOs, but from what I've seen it > _appears_ that it connects them to gnd. > > Can someone confirm this?
Heh, so Xilinx possibly violates their own rules? :) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
