Intesting. I've gotten varying results from ISE. Consider these cases:
// case 1
wire [7:0] in;
wire [7:0] out = in >> shift;
// case 2
wire [7:0] in;
wire [15:0] in2 = {8'b0, in};
wire [7:0] out = in2 >> shift;
// case 3
wire [7:0] in;
wire [7:0] in0 = shift[0] ? in[7:1] : in;
wire [7:0] in1 = shift[1] ? in0[7:2] : in0;
wire [7:0] out = shift[2] ? in1[7:4] : in1;
In each case, ISE gives me different results, even though they should
theoretically all give me the same thing. The difference between
cases 1 and 2 was very surprising to me. BTW, I was only judging them
on speed, not area.
On 6/13/05, Viktor Pracht <[EMAIL PROTECTED]> wrote:
> Am Montag, den 13.06.2005, 07:50 -0400 schrieb Timothy Miller:
>
> > > It produces 24 2-to-1 MUXes for the wires and an 8 bit register for the
> > > output. Since your code with the >> operator produces exactly the same
> > > result, I wonder what you mean with "a better way".
> >
> > You synthesized it?
>
> Yup (just the rotate, not the whole pipeline).
> Both variants result in the same number of primitives. The placing
> doesn't match exactly, but on an otherwise empty xs3s1500, 16 of the
> MUXes are close to each other in two rows in the same place, and the
> rest is distributed randomly across the FPGA.
>
>
> - Viktor Pracht
>
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