We opted to not use a special prom for the FPGA, since what's available is really expensive. Instead, we're using a cheap PROM and the Lattice part as a loader for the Xilinx. This has the added benefit of letting us use only one PROM chip for both BIOS and bitfile.
Since all that's built into the Lattice chip, along with PCI, we'll have ways to program the prom, program the FPGA from the PROM, and program the FPGA directly. On 8/12/05, Peter TB Brett <[EMAIL PROTECTED]> wrote: > > Timothy Miller wrote: > > > I'm trying to finish up PCI. There are a couble of things I need that > > I don't know how to do off the top of my head: Program the Xilinx and > > reprogram the PROM. > > I don't know if any of this will be useful: > > What we do here on our development boards is to have a PROM that's > connected to the Spartan-3 with the FPGA in master serial configuration > mode (so it gets automatically configured on start up). > > /======\--->---/======\ > | PROM | | FPGA | > \======/---<---\======/ > > The Spartan-3 and ROM also form a JTAG chain [1] (apologies for appalling > ASCII art): > > /======\ /======\ > --->-------| PROM |--->---| FPGA |----\ > ---<---\ \======/ \======/ | > | | > \------<--------------<--------/ > > So we can always configure the FPGA without touching the ROM and vice > versa, which is really useful in the "poke things until they work" stage > of design. > > Anyway, what I'm getting at is: how about writing a PCI to boundary scan > interface? It seems like the elegant solution to me... > > Peter > > [1] You can always configure a Spartan-3 by JTAG no matter what the > settings of the M(0..2) mode pins are. > > _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
