* Timothy Miller <[EMAIL PROTECTED]> [2005-08-15 16:45]: > > Let's begin by having an open discussion about what's going into the Lattice > chip. > > Since I have much of the PCI logic done, let's work on some of the other > stuff. Two things on the plate right now: (a) SPI PROM reading and writing, > and (b) how to program a Xilinx chip. > > We could program the Xilinx serially or using its parallel interface. > Probably should go with the latter if we can get data out of the PROM fast > enough. The sooner the Xilinx is online during the boot process, the better. > > Let's talk about the logic involved and how they're going to interface with > the host controller.
If you're planning on using a serial PROM I don't see any reason not to use the slave serial programming mode for the Xilinx part. I pulled up a couple of serial PROM datasheets and they all have read bitrates on the order of Kbps. Might as well save the IOs and keep it serial. Did you have any specific parts in mind for the FPGA, CPLD, and PROM? Are we going to need multiple PROMs to hold the bitfile? Reading the PROM and programming the FPGA should be pretty straightforward after part selection since the interface on both ends (Xilinx and PROM) is fully speced for us. For host reads/writes a config bit could map the PROM into the PCI address space. Other config bits could initiate reprogram cycles, etc... Are there free tools avaiable for Lattice development? The only thing I saw on their website was something to download bitfiles rather than synthesis. -Brian _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
