When Andy asked me how many pins to connect between the two FPGAs, I just asked him to give me "about 80" pins. But he would like to name them on the schematic, so I'm going to itemize them. I've sorta done this before, but let's review to make sure we don't miss anything. Speak up if you see anything missing. Also, someone should add this to the wiki.
First, there's the Lattice: (1) PCI 32-bit There are 84 pins defined, but lots of them are reserved or ground, and some others don't connect to the chip. We can itemize them here just for general interest. I won't do that just yet, because I believe Andy has that worked out. I also need to check to see if PCI-X has any extras, because for that, I have only been considering clock rate, not how the card indicates it can do the speed. The TROZ spec lists 49 (plus the 64-bit extension), but it only did target, so we'll have to add like 5 more pins to get mastering. (2) SPI PROM Andy has the spec, but I don't. (3) Local bus to the Xilinx (3.1) Address bus (out): 32 pins (3.2) Data bus (bidirectional): 32 (3.3) Byte enables (out): 4 (3.4) Access target (out): 6 (mem0, mem1, engine, Peripheral, VGA, spare) (3.5) Write queue full (in): 1 (3.6) Write enqueue (out): 1 (3.7) Request queue full (in): 1 (3.8) Request enqueue (out): 1 (3.9) Read queue empty (in): 1 (3.10) Read dequeue (out): 1 [This comes to 80] (4) Misc (4.1) Peripheral bus See below. (4.2) Clock pins The main clocks for the Xilinx will be generated in the Lattice part, presuming jitter is low enough. This probably includes the video clocks which needs a lot more flexibility. We may need external PLLs for that, though, controlled by the peripheral bus. (4.3) General I/O Whatever is left Then there's the Xilinx: (1) Memory There are eight 256 megabit chips with 16-bit busses. There are eight data busses and four address busses (data busses run at 2x speed, so we want point-to-point). These are regular DDR chips. (1.1) Memory address bus (1.1.1) Address: 13 (1.1.2) Bank: 2 (1.1.3) Chip select: 1 (1.1.4) Clock enable: 1 [17 pins each, total 68] (1.2) Memory data bus (1.2.1) Data: 16 (1.2.2) Data mask: 2 (1.2.3) Clock: 2 (1.2.4) Data strobe: 2 [22 pins each, total 176] The whole memory bus then uses 244 pins. (2) Video There are two dual-link DVI outputs, using double-data-rate. There is one digital bus that will connect to both a VGA DAC and a TV chip. Then there's something to generate raw LVDS for embedded TFT's. This section is my guesswork, and Andy and others can correct it. Note that there will be at most two controllers in OGA. Some of the extra pins are for data integrity only. I think there are two pins for DDC, and there should be one set for each interface. (2.1) DVI (2.1.1) Data: 24 (2.1.2) Vertical: 1 (2.1.3) Horizontal: 1 (2.1.4) Blank: 1 [27 pins, total 54] (2.2) Analog (2.2.1) Data: 24 (2.2.2) Syncs: 3 [27 pins, total 54 if TV has to be separate] (2.3) LVDS Presumably, we'll use an external encoder for OGD and an internal one for OGC. A single 1280x1024 head can be driven by a single LVDS encoder, so we'll just put one on here. This is a major guess here. LVDS may need more signals. (2.3.1) Data: 24 (2.3.2) Syncs: 3 Total is as many as 135 pins plus DDC for each interface, which probably adds a minimum of 6. (3) Misc Additional signals will (3.1) Peripheral bus Usually 8 to 32 data pins, plus maybe 10 address pins, plus some sync stuff. TROZ defined 24 pins for this, and I think that interface was modeled after the interface required for most RAMDACs. There will be one on either the Xilinx or the Lattice or both. But OGA will have only one, so we'll probably define two and then enable only one in the design. (3.2) I2C This is 5 pins: Data in, data out, mode, clock, enable. (3.3) Clock pins There will be some additional clock signals that are used around the board. (3.4) General I/O Whatever is left _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
