Timothy Miller wrote:
On 10/22/05, Daniel Rozsnyó <[EMAIL PROTECTED]> wrote:
So, please do not use IDE connector for GPIO (to avoid the use of
inproper cable - rather use an 50 pin variant, where anybody can get
headers and flat cables and assemble them easily).
Ok, that's fine. Is the 50-pin variant common? How about SCSI? Any
of those simple enough connectors?
Basically, whatever you guys come up with is what I'm going to
recommend to Andy. Better still if you can find the part in a
catalog. Maybe we should have a contest. Whoever identifies the
best, cheapest solution gets a free T-shirt if that's what we end up
using. :)
Ok, here are my thoughts.
I would vote for a pair of standard .1" 50 pin headers aligned such that
they would physically support a small expansion daughter board. I would
also suggest (barring board layout problems) that they be placed close
enough to the bracket on the board that the daughter board could occupy
the next PCI slot. The ultimate option would be to place a mating
connector on the back side of the OGD board to allow for multiple boards
to be interconnected. Another option would be to put right angle
headers along the top of the board. This would allow easy connection to
daughter boards or other OGD board via simple ribbon cables.
I would be my suggestion to stay away from anything other than standard
.1" headers in the first rev of the board. This does limit us in the
speed of the interconnect, but it opens it up to the widest array of
people at the lowest cost. The higher density connectors are expensive,
$5US or more in small quantities.
As far as logic level vs Differential signaling goes both has it's pro's
and cons. I would tend towards logic level for exposure reasons. It is
much easier to interface with logic level signals. I can plug the cable
directly into a proto board sitting on my lab bench and do things with
it. I can connect it to my logic analyzer and directly read the
output. In general, more people can tinker with it. It does of course
limit signal frequency and cable lengths. It also ups the power
consumption and probably the on board chip count. I don't know what the
FPGA drive capability per pin is, but I would really want the signal
buffered outside the FPGA anyway. I would much rather fry a $2 buffer
chip that I have some hope of replacing with the capabilities I have in
my lab vs destroying a very expensive FPGA.
We also don't want to over engineer this card. It needs to be simple,
cheap, and work. The more people that can buy this card and work with
it, the better off we are. Making easily usable by someone, right out
of the box, is important, especially in the education realm. Another
thing to consider is what functionality could be added later via a
daughter board? Differential signaling, for example, could be added via
a driver board.
Just my thoughts.
Patrick M
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