On Sat, 2005-11-12 at 19:41 -0500, Timothy Miller wrote: > On 11/12/05, Carl Witty <[EMAIL PROTECTED]> wrote: > > Be sure to register the outputs of your "FIFO is empty" and "FIFO is > > full" computations (and make sure your synthesis tool does not replicate > > these registers); otherwise, you may run into issues where part of the > > circuit acts as if the FIFO is empty and part of it does not. > > I've been thinking about that. I guess you're talking about a race > condition where the result of the xor maybe causes metastability in > one replication of the register and not in another and similar > conditions. That is indeed a concern. The routing to different > registers is going to be different and have potentially disasterous > effects.
You don't need metastability to get problems here; timing differences could mean that one register is solidly high and another is solidly low. And of course, metastability is a problem even with a single (non-replicated) register; one that I've never really dealt with myself (I just double-register inputs from outside, which makes metastability negligibly rare). All my designs that use multiple clock domains inside a single chip actually use different scalings of a single clock (using the Xilinx DLL and DCM modules), so the Xilinx tools can compare the various timings and phases and ensure that cross-clock-domain transfers are safe from metastability. (Is that a possibility for your design? How many clock domains do you need? Do they need to come from off-chip?) > Thank you. Your suggestions were very illuminating. Have you had a > look at the fifo code I posted? What do you think of that one? No, I haven't looked at your code, and I probably won't have time to. Carl Witty _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
