On 11/28/05, Viktor Pracht <[EMAIL PROTECTED]> wrote:
>
> I meant Verilog source for a testbench, which I can integrate into the
> petri net. Then it can run alone for a couple of days to test all
> possible states and delay combinations.
>
Ok, here's something. Right now, it's programmed to dequeue faster
than enqueue (keeps it empty). They're on different clocks. And I
just hacked in out_clock, so there could be an error, because I gotta
run before I can test it. Also, it has a time limit. One thing I/we
can do is rewrite it to try different sets of clocks, etc.
module test;
reg clock, reset, out_clock;
initial begin
clock = 0;
forever #5 clock = !clock;
end
initial begin
out_clock = 0;
forever #6 out_clock = !out_clock;
end
initial begin
$dumpfile( "test.vcd" );
$dumpvars;
reset = 1;
#50 reset = 0;
end
wire full, valid_out, empty;
wire [31:0] d_out;
reg enq;
reg [31:0] counter;
always @(posedge clock) begin
if (reset) begin
counter <= 0;
enq <= 0;
end else begin
if (!full) begin
if (!enq) counter <= counter + 1;
enq <= !enq;
end
end
end
reg deq;
reg [31:0] got_data;
always @(posedge out_clock) begin
if (reset) begin
deq <= 0;
end else begin
if (valid_out) begin
got_data <= d_out;
//deq <= !deq;
deq <= 1;
end
end
end
sync_fifo bf(reset, clock, counter, enq, full, out_clock, d_out,
valid_out, deq, empty);
initial begin
#10000;
$finish;
end
endmodule
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