Le mardi 27 Décembre 2005 02:02, Pieter Hulshoff a écrit : > On Tuesday 27 December 2005 01:50, Timothy Miller wrote: > > Is it still a problem if the reset is held active for a long time? > > That's always how I've done it. I've made sure that the reset was > > active for at least a few cycles in the slowest clock domain. > > Setting the reset is not the problem; resetting it is. When the reset > signal is reset asynchronously, some FFs may still be reset on that clock > edge, while others are updated in accordance with the code. This can create > very interesting behaviour of your design after a reset. > > > Can you get glitches if you do sync reset on a single reset signal? > > Or should we ensure that there's a valid reset for each individual > > clock domain? > > A reset should be valid for each clock domain, though as with most signals > you can just transfer it to the proper clock domain using 2 FFs. >
Where i work we use asynchronous reset with synchronous reassert. That means that you use async reset on each FF (faster, no dead lock possible...) but there is a circuit that synchronise when the reset goes up. The meta stability could come when sync reset is set or when the async reset is released. Nicolas Boulay _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
