> Maybe the chip manufacturers will play nice. We may be able to > convince them that there is revenue potential here.
Well, this project could be a pretty good argument to opening up for a lot of rather closed companies. Here's to hoping :) > But even with full documentation, there's still the issue of > developing good P&R. IIRC, icarus can produce EDIF netlists. I don't > know if it bothers to optimize them any, but you can then feed that > into P&R software and get a routed bitfile. > > What's really hard about this, though, is that everyone's going to > physical synthesis where the P&R is combined with synthesis. Wire > delays (which are dominant in modern chips) are exact, rather than > estimates. When wire delay is going to affect synthesis, the > syntesizer can take it into account and do a better job optimizing. Yeah, I wouldn't expect really good results from an open synthesis tool for years (decades). Having one that has basic functionality would be really great for hobbyists like myself though. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
