Just a short update today, nothing too heavy, I promise. See y'all soon.
- Piete.
######################################
# gEDA Schematics: Status 20060314 #
######################################
For project information including contact details, aims and objectives,
and links, please find the post "gEDA Schematics: Status 20060314".
Symbols & scripts: http://www.kaear.co.uk/ogp/
(The site is currently having some issues with directory browsing and
they've turned off my control panel - bear with me and I'll get it up soon)
##
## Status
##
As of March 14th 2006:
* Peter has kindly submitted a header-creation script called headergen.
You can find it in the scripts directory. This script is GPL'd and
copyright Sharp Laboratories of Europe Ltd.
---------------------------------------------------------------------------
Using headergen
---------------
Usage: headergen [options] <numpins>
Generate a gEDA symbol for a header or socket.
Options:
-d Generate a double-row header
-s Generate a socket instead of a header
-w Write a symbol file
-p <prefix> Prefix the pin numbers with a string
-f <firstnum> Start numbering pins somewhere other
than zero
Report bugs to <[EMAIL PROTECTED]>
Examples (run them and then view the output with gschem to see the result):
(1) Creates HEADER-2-1.sym
headergen -w 2
(2) Creates HEADER-5x2-1.sym
headergen -dw 10
(3) Creates HEADER-8-2.sym
headergen -ws 8
The -f and -p options are designed to aid in creating several files
that are spliced together to create a bigger header.
---------------------------------------------------------------------------
* buildComponent.sh has been upgraded to include other options, read the
file to find out more.
* A second version of the ECP2_50 FPGA schematic has been added, with
only one column of pins it more closely matches the symbols in the
schematic.
* The schematics do not appear to include the ground connections listed
in the [ECP2_50] datasheets. The BGA claims to be a 672 pin, there are
771 pins listed in the datasheet.
Breakdown (according to the datasheet)
VCC 20
VCCAUX 16
VCCIO 5 per bank (except bank 8 which has 2)
GND 72
NC 3
If I grep the file made from the list (not from the tables provided) of
pins, I get:
VCC 131 ((20 + 16 + (5*8) + 2)) = 78!!
GND 126 != 72
The schematics appear to use the datasheet tables and remove the VCCs
and GNDs from each bank. Why they include VCCs and GNDs in the
connector list in the first place if they fail to give a ball number is
totally beyond me.
##
## Next step
##
* Amend the signal list and rebuild the ECP2 fpga.
* Create the smaller LatticeXP and DRAM symbols and sanity check these
against the schematics.
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