On 3/17/06, Jack Carroll <[EMAIL PROTECTED]> wrote: > On Thu, Mar 16, 2006 at 09:09:04PM -0500, Timothy Miller wrote: > > > > Unfortunately, our DACs don't take more than 8 bits per channel. > > > Time permitting, this may be worth revisiting. If some OGD boards > will be used to check out logic for an OGC installable option that supports > higher-resolution video DACs, it might be necessary to provide a hardware > platform to test the Verilog logic on. If the feature is to be tested at > all, an OGD2 board is probably too late for the ASIC.
This is a simple matter of not having enough pins on the FPGA. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
