On 4/14/06, Timothy Baldridge <[EMAIL PROTECTED]> wrote:
On the discussion about GPUs for OGP:
Here is an off the wall idea a friend and I were talking about a while
back. I think that it would be of great use in a GPU. The idea is to
create a "modularized" RISC processor. Here is a basic rundown:
The CPU accepts 3 instructions:
load
store
mov
This probably sounds dumb, in fact it probably is dumb, but I don't really see the need for an instruction op-code at all? If EVERYTHING the GPU has access to is memory mapped, why not just make each "instruction" a pair of addresses? (or a set of addresses, however wide you want your processor to be).
This sounds to me like it has big potential, but the thing that will limit it is your memory bandwidth. How quickly can you load a pair of 16-component vectors from memory and feed them to a bank of 16 ALUs? If it will take 32 cycles, you haven't gained a lot. If, OTOH, you have a 512-bit bus to your memory and can load 16 x 32-bit floats each clock cycle, then you are on to the good stuff.
If you implement it in FPGA, you could also have a reprogramming mode where some app knows what optimized instructions it needs, and knows how to load new modules into the FPGA... of course context switches will get messy.
Tom
_______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
