On Wednesday 19 April 2006 10:07, Nicolas Boulay wrote: > > Le mardi 18 Avril 2006 22:33, Lourens Veen a écrit : > > What if all the functional units had the same latency, that is, > > they all have a fifo on their output that increases their latency > > to some common maximum M. Scheduling would become trivial, you just > > generate the instructions in order, and then interleave M copies of > > the code. There are always M identical instructions in a row so you > > only need to load a new instruction every M clock cycles. ILP could > > be achieved through having multiple MISC cores, if the compiler > > makes sure that they don't access the same functional unit at the > > same time. > > > Latency is usualy a killer. Pipeline is used to keep the speed high. > Imagine a 1 cycle, 3 clock latency FMUL beside a 32 cycles divider. > Then you could add the problem with loop and if condition. > > As said by Timothy, we need hand compile code.
Ah, I hadn't thought of branching. Never mind then... Lourens
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