Apparently, the ECP2 has some special I/O buffers especially for DDR memories. Not only are there DDR I/O buffers, but there is a mechanism for setting the clock phase angle properly. With Xilinx, I had to do weird stuff like make a DCM put out a clock at a 90-degree offset, but Lattice does this for us.
Here's the app note I found on this: http://www.latticesemi.com/dynamic/view_document.cfm?document_id=19040&jsessionid=ba309813fe96$18$3F$3 I wouldn't say that this is impenetrable, but the diagrams leave me wondering exactly how to instantiate this in code. It's a bit confusing. I'm also not entirely sure how to do read and write at the same time. :) I asked a Lattice rep for reference Verilog code, but the response was that there won't be any for the forseeable future. The suggestion was to use their IP generator to make one, but this isn't something I can release under GPL (it doesn't even generate any actual RTL), and besides, all of the timing numbers are constants, while I want them to be programmable. Anyone willing to have a look at the app note and help me figure out how to hook up the modules properly? Thanks _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
