On 5/29/06, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
After initial turnaround of simulations and agreeing on some architecture we could use SystemC.
Looks interesting. Can we convert SystemC to Verilog for final synthesis? _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
