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Timothy Miller wrote:
> On 6/10/06, Hamish <[EMAIL PROTECTED]> wrote:
>>
>> What exactly doesn't it like about the code? Is it somply
>> complaining because there's two (Almost) identical always blocks
>>
>> always @(posedge clock) SCK_reg <= #1 1; always @(negedge clock)
>> SCK_reg <= #1 CE_;
>>
>> Which both assign to SCK_reg? In which case it doesn't seem to
>> understand that (presumably) SCK_reg should be assigned 1 on the
>> rising edge of the clock, and CE_ on the falling edge...
>>
>> Do I read it correctly? And what should be the way to specify an
>> action on the rising or falling edge of the clock in verilog?
>>
>> [Sorry. Just wondering really if I'm reading this correctly].
>
> There isn't one in Verilog.  For synthesis, you cannot assign to
> the same net or register from two different places, and there's no
> construct for assigning on two edges.  (Although, you can assign to
> A on pos, B on neg, and then mux them together, but that's not what
> we want.)  I had given this as a simulation-only example, but
> Petter put it in his code directly.
>
> The solution is to use a DDR flipflop I/O buffer, and the correct
> one for Lattice is this:
>
> ODDRXC ddr_ff  (.CLK(clock), .DA(for_rising), .DB(for_falling),
> .RST(reset), .Q(to_pin));
>

I understand some of that statement... But not fully... You couldn't
tell me exactly how that works could you? (It's the verilog syntax
that I don't get, not the concept of using the FF).

Especially the slightly different

ODDRXB sck_buf (.DA(1'b0), .DB(CE_) , .LSR (1'b0), .CLK (clock), .Q
(SCK));

that appears in the code... What's the diff between ODDRXB and ODDRXC?
And the .LSR is what?

Sorry. I don't have a verilog reference yet... Amazon (.co.uk) don't
seem to have any that I can find that are particularly relevant...
Except where they're several hundred pounds...


regards
  Hamish.

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