Am Donnerstag, den 15.06.2006, 22:21 -0400 schrieb Timothy Miller:
> Next, there's the raster-op (ROP). Given any two bits, there are 16
> ways to combine them. These include the basics like AND, OR, and XOR,
> but also things like src-only (copy), dst-only (no-op), invert (~dst),
> copy-invert (~src), and the degenerate cases clear (0) and set (all 1
> bits).
>
> Since there are 16 ROPs, we can use a 4-bit number to express them.
> Have a look in "/usr/include/X11/X.h" and search for GXcopy. You'll
> find names for all 16 rops and their numbers.
>
> The easiest way to express this in hardware is to concatenate the two
> bits together into a 2-bit number and use that to mux amongst the four
> ROP bits. If you don't see this right away, don't fret. I didn't
> either. I suggest you play about a bit with ROP numbers and input bit
> values and see it in action. Also, we're using the mux a bit
> strangely. Usually, we have inputs to the mux and some number to
> select amongst them on the select input. In this case, the "inputs"
> are a constant, and the pixel bits are being used as the select
> inputs. Here's the behavioral logic for that:
Here's an alternative way to explain this, which may make it more clear
for some. This is not intended to be part of the Verilog lessons because
it teaches no Verilog, just how the ROP and FPGA LUTs work.
The way that boolean logic is introduced is with truth tables. A truth
table contains a column for every input and output. For every possible
combination of input values, it contains a line describing output
values. Some examples:
. a | b | (a AND b) a | b | (a OR b)
. ---+---+----------- ---+---+----------
. 0 | 0 | 0 0 | 0 | 0
. 0 | 1 | 0 0 | 1 | 1
. 1 | 0 | 0 1 | 0 | 1
. 1 | 1 | 1 1 | 1 | 1
Inputs are listed before the outputs. In the examples above, the first
two columns are the inputs, the third column is the output.
In general, any piece of digital hardware without
registers/flip-flops/latches (i. e. where the value of the output
depends only on the current input values) can be described by a truth
table. This is also the trick behind FPGAs: if you can implement truth
tables, you can implement any combinatorial logic _and_ change what
logic you implement by changing the contents of the truth table. Add
plenty of registers and you can implement any hardware you want.
The implementation of truth tables in FPGAs is called look-up tables, or
LUTs. Each LUT is just a small piece of RAM. The inputs are used as the
address to select the right line of the truth table. The RAM content at
the selected address is the value of the output. Since FPGA LUTs usually
have 4 input bits and one output bit, you get a 4 bit number as address,
which results in 2^4 = 16 adresses and a 16x1 bit RAM for each LUT.
LUTs are also used to implement the raster operations (ROPs) in graphic
cards. You have two input bits (src_bit and dst_bit) and one output bit
(result_bit). When looking at the concise version of the implementation:
> wire result_bit = rop[{src_bit, dst_bit}];
you see (assuming we've already know registers) that rop is nothing
other than a 4x1 bit RAM, with the combined inputs {src_bit, dst_bit}
used as the address.
There are exactly 16 possible ROPs, because that's the number of
possible different RAM contents of the ROP LUT: 4x1 bits can have
2^(4*1) = 16 different combinations. In general, with x inputs and y
outputs, you have a (2^x)*y bit RAM and 2^((2^x)*y) possible functions.
- Viktor Pracht
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