On 6/16/06, Vinicius Santos <[EMAIL PROTECTED]> wrote:
Even though it sounds silly, I was trying to play around with
constructing a simple async memory. So I build this module:
// 128KB Memory
// 16 bit addressing, 16bit word
module memory (input [15:0] addr, input [15:0] in, input write, input
read, output reg [15:0] out);
It would be nice if Verilog syntax were that concise. Here's what you need:
module memory(addr, i, write, read, out);
input [15:0] addr, in;
input write, read;
output [15:0] out;
reg [15:0] out;
[It occurs to me that a more recent dialect of Verilog might support
the syntax you're using. Is that what you did?]
reg [15:0] mem [65535:0];
always @ (read,addr)
begin
if(read) out = mem[addr];
end
We wouldn't normally do it this way, but this is a good model of an
async memory. The out reg would resolve to a latch. A flipflop is
edge-sensitive to a clock. A latch is level-sensitive to an enable.
The enable here is the read signal.
always @ (write,addr)
begin
if(write) mem[addr] = in;
end
On the other hand, I don't know if this would work at all for
synthesis. We'll see how to handle this when we get to
synchronous/sequential logic.
Of course, it would work fine in simulation.
endmodule
And a test module:
module memory_test();
reg [15:0] addr = 0;
reg [15:0] in = 0;
wire [15:0] out = 0;
reg write = 0,read = 0;
I don't know what it means for you to have initializers for the regs
like this, and the wire is an output, do definitely don't assign it
anything.
initial begin
$monitor("%g write=%b read=%b addr=%h in=%h
out=%h",$time,write,read,addr,in,out);
end
initial begin
read = 0;
write = 1;
in = 16'hff00;
addr = 3;
#1;
read = 1;
write = 0;
addr = 3;
end
memory A (addr,in,write,read,out);
endmodule
But I got the following output when executing a.out:
0 write=1 read=0 addr=0003 in=ff00 out=xxxx
1 write=0 read=1 addr=0003 in=ff00 out=xx00
I assume those 'x' means 'Don't Care', but why am I getting those?
It's even strange because it sets 0 accordingly.
x sometimes means don't care, but in this case, it means "unknown" or
"uninitialized".
Anyhow, I think what's happening here is that "out" has two drivers.
For the bits where they agree, you're getting the zeros, but when you
try to set it to 'h0000 and 'hff00 at the same time, you end up with a
conflict, and that's why, I think, you're getting x's.
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
