Howard, Andy, and I did our due dilligence on the OGD1 design to make
sure that it was really going to meet our needs.  To test that we
would be able to fit an OGA-compliant design into the ECP2-50, we
cobbled together a resource-equivalent "design" from pieces from old
designs we'd done in the past.  We blew the resource count by a
significant margin.  Our determination is that the 3S4000 is the only
chip available within the next 6 months that will meet our needs, so
we're switching back.

Some results of this change:
- About two weeks setback in OGD1 PCB design schedule
- 10-bit triple-DAC fully connected
- Some extra user I/O signals
- Potentially wider local bus between the two FPGAs
- More versatility on the signal types for the user I/Os
- Increase in OGD1 parts cost
- Potential to populate 3S5000, if necessary
- Some challenges with having to use ISE 6.3i to syntesize for the 3S4000.
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