from OGPN8, there was mention of the start of coding and the need for an
SPI module. I hacked one together which appears to work(at the bottom),
at least in Icarus (ISE was so much more hassle, and iverilog *actually*
runs in Linux).
I'll be happy to continue work on it, and anything else that isn't too
complicated (e.g. don't put me in charge of the Rasterizer :-)).
I have a few questions about this module:
1) I could add in support for writing to/from addresses on THIS flash
module (SST25LF020A/040A), but right now it doesn't. I should probably
add WP/HOLD pins if I do.
2) Does anybody have a link to the actual SPI standard? or should I just
follow whatever the SST25LF020A/040A data sheet says? I just have it
clocking serial data currently, with no CS pin, etc, doing anything.
3) what interface should I have to other modules? (e.g. what wires
should be inputs/outputs from this SPI unit) Just data, address,
clock,PLL? Anything else?
Like I said, all it worries about is the actual serial part right now,
but the rest shouldn't be too hard. Down at the bottom, you can change
the sent/received value using the datas=42 line (Hitchhiker's Guide
reference). Just change it to whatever, at it should work (less than 256
and greater than 0!). Also, you can the #100 $finish line to a larger
number in order to run longer.
So, please "describe in detail the interface and how it will be
used" :-)
Naming scheme:
Of course, I can change this, but what I have right now is the wire
versions of things are what you expect, and the registers have an S on
the end (for Stored). so clk==clks, data==datas, etc. They are all
assigned. I am going to try to get a clock pin working for the data, so
that you just latch it on, but it shouldn't really matter in logic
(since everything is parallel). Finally, there is WAY too much debugging
output, but it gives you the idea.
module SPI (data, cs, sdi, sdo, sck, ready, pll, dataout);
input [7:0] data;
output cs; //Chip Selects
output sdo; //data out
input sdi; //data input
output sck; //clock
output ready; //ready for more
input pll; //the PLL clock input, whatever freq it is it is too much
output [7:0] dataout; //the input recieved from the SPI slave
wire [7:0] data;
wire cs;
wire sdi;
wire sdo;
wire sck;
wire ready;
wire pll;
wire [7:0] dataout;
reg [7:0] databuf; //data buffer - to sdo
reg [7:0] datain; //stuff latched off of sdi
reg intclk; //internal clock for timing SPI
reg [2:0] bit; //which output bit we are on
reg [7:0] divide; //the baud rate divider
reg [7:0] inc; //the compare register for baud rate
reg readys;
reg sdos; //these two store the value to be assign'd
assign ready=readys;
assign dataout=datain;
assign sck=intclk;
assign sdo=sdos;
initial begin
databuf=0;
datain=0;
intclk=0;
bit=0;
divide=2; //divide by 2
inc=0;
readys=1; //ready to get data
sdos=0; //start off low
end
always @ (posedge pll) //when we have data latched in...
begin
readys=0;
databuf=data;
end
always @ (posedge pll)
begin
inc=inc+1;
//$display("%d pll -> %d",$time,inc);
if (inc==divide) //if we are at the baud rate...
begin
sdos=databuf[bit];
intclk=~intclk;
inc=0;
//$display("%d flop",$time);
end
end
always @ (posedge intclk)
begin
$display("%d sent bit number %d:%b",$time,bit,databuf[bit]);
end
always @ (negedge intclk)
begin
datain[bit]=sdi;
bit=bit+1;
if (bit==8)
begin
readys=1;
bit=0;
databuf=0;
end
end
endmodule
//module SPI (data, cs, sdi, sdo, sck, ready, pll, dataout);
module test();
reg [7:0] datas;
reg plls;
reg sdis;
reg [2:0] bits;
wire [7:0] data;
wire enable;
wire [7:0] dataout;
wire pll;
wire cs;
wire sdi;
wire sdo;
wire sck;
wire ready;
assign data=datas;
assign pll=plls;
assign sdi=sdis;
SPI u0 (data,cs,sdi,sdo,sck,ready,pll,dataout);
always begin
#1 plls = ~plls;
end
always @ (posedge sck) //posedge read data
begin
$display("%d got bit: %b",$time,sdo);
sdis=datas[bits];
bits=bits+1;
end
always @ (posedge ready)
begin
$display("%d got byte %b",$time,dataout);
end
initial begin
bits=0;
plls=0;
datas=42;
$display("%d -> %b",datas,datas);
//$monitor("%d got byte %b",$time,dataout);
#100 $finish;
end
endmodule
nick
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