On 7/3/06, Dieter <[EMAIL PROTECTED]> wrote:
> > > Do you (or anyone) have any thoughts on JRT's suggestion of using a
> > > DSP chip? The decoder needs to handle the most common formats,
> > > mpeg at the very least, to avoid transcoding. Transcoding takes a
> > > lot of CPU, and Theora is lossy.
> >
> > True. What would be nice would be a CPU with a built-in DSP, so that the
> > CPU can handle the network stuff and OSD and so on, and the DSP could
> > do the heavy-duty decoding work.
Timothy> How "realtime" does this need to be? Can we not implement the
Timothy> networking stuff on the DSP?
Realtime requirements probably vary with Ethernet chip?
Maybe. How fast do we expect the DSP to be? We can play some tricks
that the Linux kernel does and switch to polling (rather than
interrupts) when the network load gets too high. If we're not fast
enough to take the network traffic, packets will get dropped and then
retransmitted again by the sender.
Timothy> I'm planning on implementing RGB <-> YUV conversation, at least.
Timothy> Rather than spending bunches of CPU time doing the matrix algebra, we
Timothy> can do it in hardware and save at least SOME converstion time.
IIRC, OGC will also do scaling. Anything else it can offload?
The engine will do scaling. No plans to have the video controller do
it. Have a look at the design and see if you can suggest changes that
would allow for scaling. Integer scaling (simple pixel replication)
isn't so hard, but if you want smooth scaling, our video controller
isn't cut out for it, so we have to use the drawing engine to
prescale.
If OGC can't offload enough, are there HD mpeg decoder chips that we
could consider? (e.g. documented)
When OGD1's been out for a while, and we've gotten pretty far into the
GPU design, we should have a look at what kind of peripheral I/O the
ASIC should have for support of things like mpeg decoder chips. This
should be a low-priority item.
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