You can find the latest version of the memory controller logic here:
https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/mem_ctl/tims/ Not all of the files are still used (we'll clean it up later), but look at the "makeit" script to see which files are being used. The "runsim" script automates simulation with Icarus and signal view with GTKWave. You can see a history of versions of the fsm part of the memory controller. fsm2 is a redesign of fsm, and fsm3 is a redesign of fsm2. fsm4 is just a speed optimization of fsm3, so fsm3 is checked in as documentation. The memory controller is broken up into the following stages: - [buf] Disconnects the internal state machine busy signal from outside logic. - [rh] Two stages that constitute primarily row-hit detect logic - [fsm] Two stages that constitute the primary state machine that manages commands to the memory chip, timing delays, reads, and writes. There is some additional pipelining that brings latency for writes to 5 cycles and latency for reads to somewhere around 12 cycles (depending on CAS latency and phase differences between command clock and read clock). However, the delays are often much longer due to the need to open and close memory rows before read and write commands can be submitted. In Xilinx Spartan 3 FPGAs, I have found this design to run at 200MHz or better when it's synthesized in isolation. When we add pin constraints and other logic, Also, the fifos have been optimized for performance: https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/fifos/ Things we could use help with: - Augment the test environment, adding more stressful tests - Add a model of a DDR memory (write a simple one or get a commercial model to simulate with Icarus). - Document the design, as well as add in meaningful comments. Any takers? Don't be intimidated by the fact that this is in Verilog. There is stuff there for you to work from, so it's more like tweaking than new coding. Thanks. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
