Perhaps a memory controller is a bit complex of an example for Verilog
beginners to sink their teeth into.  So how about we work on something
practical together that is relatively easy for people to follow.  Lots
of people can and should participate.  At the very least, I suggest
that people watch and ask questions.  I consider even the "dumbest" of
questions to be genuine participation that everyone can learn from.
(Argh.  I'm starting to sound like my professors.)

What I want to put together here is a test suite for video.  The
objective is to ensure that the PCB (of which we already have a
nearly-populated prototype) is wired correctly, in that the right FPGA
pins are connected to the right pins on the DACs and DVI transmitters,
etc.  Most likely, the problems we would find are related to signal
integrity issues, rather than something being logically miswired, but
we want to check that too.  Using the video controller Patrick and I
worked on would add too many variables and too many things to debug.
What we need here is the simplest possible logic that will put
meaningful signals out video.

Here are some examples of tests I can think of, and I invite others to
suggest more:

1. Wiggle individual signals in a way that lets us examine them on a scope.
1.1. Oscillate sync signals to ensure they reach the video connector cleanly.
1.2. Oscillate analog video signals (R, G, and B) in sine and/or
triangle wave patterns to ensure signal integrity and ensure we have
all of the bits in the right order.
1.3. Oscillate analog video signals rapidly between highest and lowest
to check frequency response.
2. Output a real video frame
2.1. Just syncs with constant data (all white screen)
2.2. Ramp (left edge is black, right edge is white)
2.3. Other test patterns like a box with an X in it the size of the screen.

Note that all of these are fixed patterns.  There's no memory
involved.  Just video signals.

So, to begin with, how about someone give me the raw timing numbers
for, say, [EMAIL PROTECTED]  Shortly, I'll provide a module header for the
video pins on the two interfaces.
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