There are limits to how creative I can be in testing this thing, but I believe I have completed and debugged a PCI target that I can start converting to a synthesizable form for OGD1. In the process of testing the target, I've also written a master that is 90% of the way there to being a reference design for the master we'll use in OGD1.
I'd wanted to hook it up to the OpenCores design for further testing, but I've run out of time. Classes start on the Jan 3, and I have other work I've neglected. This is one thing I could REALLY use some assistance with. What we should do is hook up the full OpenCores design to our target, and use their bus master to test our target. There are also other tests to be written. If I could get some help with those, I'd appreciate that very much too. I've tested both the target and master in some rather unusual circumstances, some of which shouldn't happen, but which we should be prepared for. Now it's time to simulate something a bit more real-world with more typical latencies and throughputs. And all of this has to be done before we hit silicon, because it's going to be much easier to debug a simulation model than a highly optimized synthesizable one. That is, unless someone out there has a mobo that's tweaked to run PCI at like 1MHz. :) -- Timothy Miller http://www.cse.ohio-state.edu/~millerti _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
