On 1/3/07, Patrick McNamara <[EMAIL PROTECTED]> wrote:
> We have 40 bits to play
> with and 32<n<64 signals that can change. That means we can encode 6
> single-bit changes plus something else in the remaining 4 bits every
> cycle. Since n<64, we can use unassigned codes to indicate things
> like timestamp advancing, no change, etc.
Don't forget all the control signals and interrupt lines as well.
Yeah. Excepting the case of a 64-bit PCI bus (which we could
support), we have fewer than 64 signals to track.
> We may be able to take advantage of the fact that recently changed
> signals are extremely unlikely to change again.
In a properly working PCI bus, this is true. Since we are trying to debug a
card or bus here, we have to assume that the bus will be misbehaving in the
worst possible way: a glitch in the TRDY logic, for example, or perhaps some
problem in the output logic that cause the data bus to change states several
times before settling to it's final value.
>If things change too
> fast, the effect will be that we report that a signal changed 2.5ns
> later than it actually did.
This is fine as long as it is deterministic. We can pipeline the hell out of
the capture logic so long as we can always determine the time slot from which a
particular sample comes.
Patrick M
--
Timothy Miller
http://www.cse.ohio-state.edu/~millerti
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