> As for Daniel's idea: > Rather use a FIFO where the input is fed by 10x oversampled PCICLK and > output is read as fast as the transport link allows with given encoding > (transmiting changes only). It should work with a buffer for 10 samples > and you need at least half or less of the transfer rate of input, > because the signals somewhere MUST stay stable (otherwise we're talking > about 330MHz "noise" on all lines). These stable levels on input will > allow to clear the buffer, and they will occur once per PCICLK period. > > I think that this makes sense. Not only does this make the program "real > time" > and therefore drastically reduce the download time, but it also allows > for greater > flexibility in capture time. Essentially an infinite buffer (the hard > drive) is on the > tracer machine, so we might as well store the signals there. The > developer must > have two computers anyway (one test with both ODG cards, one tracer), > and this > means we can essentially use both FPGAs to implement whatever compression > we want. It is a simple matter of sending data over the UART in "real > time". The > signals are still coming in faster than we can shove them out, but as > daniel said > there is no way that 330 Mhz noise is omnipresent on the bus (at least, > I should hope not...) > > Thoughts?
Just that the above quote was not about the download, but the capture and transfer of PCI dump between XP10 and Spartan. The FIFO is inside XP10. (If you just compare the speeds, we are capturing ~ 10B @ 330MHz, the real information is somewhere at 10B/33 MHz ... ~ 330MB/s, thats far beyond any standard PC interface) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
