Tonight or some time tomorrow, I'll check in a rewritten PCI target that is designed to be synthesizable. I have to run it through more testing to make sure I didn't break anything in the rewrite, but in simple tests, it still works. In the process, I noticed and fixed some weirdnesses and inconsistencies, so this one won't be clock-for-clock identical for the simulation model. It may be appropriate to back-port the changes into the simulation model. The synthesizable version is truly an unreadable sight to be beheld. No amount of commenting will make the code "easy to understand," to anyone, even myself, and I wrote it.
I've done my timing analysis using the Xilinx tools (because that's what I have for Linux), and for a Spartan 3, the best it can do is about 75MHz. This all comes down to I/O buffer delays, and it'll be better or worse in the Lattice part, depending on how fast its I/O buffers are. Howard may be able to work some magic to improve things a little further, but the only effect will be to make it easier to hit 66MHz when more logic is included in the same chip. Because the hopes of doing 133MHz are shattered, I'm sorely tempted to try to remove the extra wait state on address decode. It'll make PIO accesses slightly faster. On the other hand, since we generally discourage PIOs anyway, in favor of DMA, I'm not sure I should even worry about it. -- Timothy Miller http://www.cse.ohio-state.edu/~millerti _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
